There is a trend to downsize packages along with recent evolutions of semiconductor devices involving increase of the operation speed and large-scale integration. One of known technologies for package downsizing is a surface mount type ball grid array (hereafter abbreviated to BGA) in which solder balls are arranged on a package substrate.
There are two types of BGA semiconductor devices having a semiconductor chip mounted on a BGA package substrate. One is a semiconductor device in which a pad functioning as an electrode for the semiconductor chip is adhesively fixed on a package substrate in a face up state, and the pad is connected to a surface layer wiring line on the substrate by means of bonding wire, and the other is a semiconductor device in which a bump or a tape lead formed as an electrode on a surface of the semiconductor chip is connected to a wiring pattern formed on the upper surface of a package substrate in a face down state. The former type of semiconductor device is described for example in Japanese Laid-Open Patent Publication No. H11-163201 (patent document). This patent document points out that, when this type of BGA semiconductor device is exposed to temperature change, there occurs breakage in surface layer wiring lines at a position on a package substrate intersecting with a visible outline defined by an end of a semiconductor chip disposed on the package substrate. This wiring breakage tends to occur in a region where a long side of the semiconductor chip intersects with the wiring. The patent document discloses, as a countermeasure against such wiring breakage, that the wiring breakage can be prevented by increasing the width of wiring in a region crossing the long side of the chip.
As for the latter type of BGA semiconductor devices, a type of BGA package in which a semiconductor chip is fixed to a package substrate by flip-chip connection while no underfill is disposed between the chip and the substrate will be effective countermeasure for avoiding the breakage of substrate surface layer wiring lines as pointed out by the patent document.
For the purpose of package downsizing, a multi chip package (hereafter abbreviated to MCP) has been developed, in which a plurality of chips are mounted on a package substrate in a two-dimensional or three-dimensional fashion, or package substrates having a chip mounted thereon are stacked three-dimensionally. The three-dimensionally stacked MCP is particularly effective for package downsizing. In the course of development of package stacked MCPs having packages stacked three-dimensionally, the present inventor has newly found an unenvisaged problem caused by wiring breakage.
Referring to FIGS. 1(A), 1(B) and 1(C) showing a semiconductor device to be discussed, signal balls 4 are disposed in a region defined by a contour 11 formed by a substrate chip, whereas support balls 5 support an overhung portion of the package substrate extending outside of the region defined by the contour formed by the chip. This means that the support balls ensures transverse strength for the package and increases its mechanical strength. In FIG. 1 (A), two support balls 5 are disposed at each of four places on the short sides of the package substrate 2.
A temperature cycle test conducted on a semiconductor device having a chip mounted on this package substrate revealed that wiring breakage would occur in package surface layer wiring lines 6(B) located in the vicinity of the support balls 5. There was found no wiring breakage in package surface layer wiring lines 6(A) not in the vicinity of the support balls 5. The wiring breakage was observed in the vicinity of the support balls 5 and in the region indicated by oblique lines in FIG. 1(B), which is an end of the semiconductor chip facing the support ball 5. Thus, it was found that the portion indicated by the oblique lines constitutes a wiring breakage prone region 10. Such wiring breakage will cause malfunction of the semiconductor device.